High-density nonvolatile memory and methods of making the same

ABSTRACT

Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.13/195,518, filed Aug. 1, 2011, now U.S. Pat. No. 8,383,478, which is adivision of U.S. patent application Ser. No. 12/477,216, filed Jun. 3,2009, now U.S. Pat. No. 8,004,033, which is a division of U.S. patentapplication Ser. No. 11/401,073, filed Apr. 10, 2006, now U.S. Pat. No.7,557,405, which is a continuation of U.S. patent application Ser. No.10/855,775, filed May 26, 2004, now U.S. Pat. No. 7,026,212, which is acontinuation of U.S. patent application Ser. No. 10/326,470, filed Dec.19, 2002, now abandoned, each of which is incorporated by referenceherein in its entirety for all purposes.

BACKGROUND

Integrated circuits are typically fabricated in monocrystalline siliconsubstrate. This substrate is expensive, leading to continual efforts tofabricate more circuitry within a given area of substrate, increasingdensity.

For nonvolatile memory, a highly effective approach to increase densityis to build monolithic three dimensional memories above the substrate,like those disclosed in Johnson et al. U.S. Pat. No. 6,034,882; Johnsonet al. U.S. patent application Ser. No. 09/928,536, filed Aug. 13, 2001,now U.S. Pat. No. 6,525,953; Knall et al. U.S. Pat. No. 6,420,215; andVyvoda et al. U.S. patent application Ser. No. 10/185,507, filed Jun.27, 2002, now U.S. Pat. No. 6,952,043, all hereby incorporated byreference in their entirety.

Such memories can be improved to achieve higher densities.

SUMMARY

In an aspect of the invention, a method is provided for forming amonolithic three dimensional memory array. The method includes: (a)forming a first plurality of substantially parallel, substantiallycoplanar conductors above a substrate; (b) forming a first plurality ofsemiconductor elements above the first plurality of substantiallyparallel, substantially coplanar conductors; and (c) forming a secondplurality of substantially parallel, substantially coplanar conductorsabove the first plurality of semiconductor elements. Each of the firstplurality of semiconductor elements includes a first heavily doped layerhaving a first conductivity type, a second lightly doped layer on and incontact with the first heavily doped layer, and a third heavily dopedlayer on and in contact with the second lightly doped layer. The thirdheavily doped layer has a second conductivity type opposite the firstconductivity type. Numerous other aspects are provided.

BRIEF DESCRIPTION OF THE DRAWINGS

Features of the present invention can be more clearly understood fromthe following detailed description considered in conjunction with theappended claims and the following drawings, in which the same referencenumerals denote the same elements throughout, and in which:

FIG. 1 a and FIG. 1 b illustrate three dimensional memory cellsaccording to the present invention;

FIG. 2 a through FIG. 2 d illustrate prior art device fabrication;

FIG. 2 e and FIG. 2 f illustrate viewing planes used in FIG. 4 a andFIG. 4 c;

FIG. 3 a through FIG. 3 c illustrate etch undercut;

FIG. 4 a through FIG. 4 c illustrate stringer formation;

FIG. 5 a through FIG. 5 c illustrate misalignment between conductors andan overlying semiconductor element;

FIG. 6 a and FIG. 6 b illustrate spacing of the semiconductor elementsin two dimensions;

FIG. 7 illustrates cross-sections of example shapes having substantiallycylindrical shape; and

FIG. 8 and FIG. 9 illustrate contact formation according to the presentinvention.

DETAILED DESCRIPTION

Johnson et al. and Knall et al. both disclose monolithic threedimensional memories which provide for high density memory arrays. Thepresent invention provides for creation of a monolithic threedimensional memory with a structure similar to those disclosed inJohnson et al., but uses a different method of fabrication and differentchoice of materials, allowing for improved density, performance, andease of manufacture.

The structure of a single memory cell 2 of the present invention isillustrated in FIG. 1 a. At the bottom is conductor 4. Above conductor 4is semiconductor element 6, and above that is conductor 8. In thepresent invention, semiconductor element 6 is substantially cylindrical,for reasons that will be described below. The memory cell of Johnson etal. has a similar structure, but its semiconductor element, called apillar, is not substantially cylindrical. Turning to FIG. 1 b, in boththe memory of Johnson et al. and the present invention, anothersemiconductor element 10 can be formed above conductor 8, and anotherconductor 12 above semiconductor element 10. Conductor 8 then serves asthe top conductor for the lower memory cell 2 and as the bottomconductor for an overlying memory cell 18. Memory cells may be stackedvertically several stories high.

The methods of fabrication described by Johnson et al. to form an arrayof such memory cells make use of self-alignment. As shown in FIG. 2 a,the first conductor material 46 and first semiconductor layer stack 45are deposited. Both are patterned and etched in a first etch to formsubstantially parallel first conductors and first etched lines ofsemiconductor layer stack in a single masking step, the resultingstructure shown in 2 b. Note that the semiconductor layer stack has beenetched at this point into lines 45 a and 45 b, and not yet into pillars.The gaps between the lines of semiconductor layer stack and theconductors are filled with dielectric material (not shown) to insulatethe wiring and devices from one another. Next, in FIG. 2 c, the secondconductor material 50 and second semiconductor layer stack 51 aredeposited, then are patterned and etched in a second etch to formsubstantially parallel second conductors and second etched lines ofsemiconductor layer stack which are substantially perpendicular to thefirst conductors. As shown in FIG. 2 d, the second etch continues pastthe second conductors and etches through the first lines ofsemiconductor layer stack, forming first semiconductor pillars such as45 a 1 and 45 b 1, leaving the first pillars with substantiallyrectangular cross-sections. The insulating dielectric is not etched.Because they were formed in a shared masking step, two opposing sides ofeach of the first pillars (e.g. 45 a 1) are self-aligned with the edgesof the first conductor below (e.g. 46 a), while the other two opposingsides of each of the first pillars are self-aligned with the edges ofthe second conductor above (e.g., 50 a.) The gaps in between the secondconductors and second lines of semiconductor material are filled withdielectric material.

Use of self-alignment allows for a minimal number of masking steps perdevice layer. Self alignment eliminates the spatial error that occurswhen one layer is independently aligned to the layer below, allowing forsmaller feature size. Feature size is the minimum dimension of elementsin a cell.

As this process is scaled to still smaller feature size, however, twochallenges come to the fore. First, as feature size gets smaller,conductors and pillars get thinner and move closer together, causing theaspect ratio (ratio of height to width) of the gaps between features toincrease. When the aspect ratio exceeds about 7:1, it becomes difficultto reliably fill gaps with dielectric material using conventionaltechniques without creating voids in the fill. These voids can be fatalto device performance.

Another problem is that of etch undercut that occurs when etching a filmstack consisting of several different materials. FIG. 3 a illustrates astack of materials to be etched. In this example, the stack consists ofa layer of polycrystalline silicon 82 (also called polysilicon), TiNlayer 84, TiSi₂ layer 86, and polysilicon layer 88. Photoresist layer 80is patterned on top, and all of the layers below are etched. Etchselectivity, which describes the etching rate of one material relativeto the etching rate of another material, between polysilicon and TiSi₂is poor, so while polysilicon layer 88 is being etched, TiSi₂ layer 86is unintentionally etched as well, as illustrated in FIG. 3 b. That is,as the polysilicon in polysilicon layer 88 underneath the TiSi₂ layer 86is being etched vertically, the TiSi₂ of TiSi₂ layer 86 is etchedlaterally.

Such undercut can damage device performance. As feature size decreases,the width of the stacks to be etched decreases. The height of the stackis unchanged, however, so the time required for etch and the amount ofundercut is also unchanged. The same absolute amount of undercut on anarrower stack results in a larger percentage undercut, as shown in FIG.3 c.

By recognizing the aspect ratio and undercut problems and solving themthrough process changes and choices of material, the present inventiondecreases the minimum feature size achievable in a monolithic threedimensional memory. The present invention decreases aspect ratio byusing different fabrication methods, and minimizes etch undercut byusing different materials.

The present invention affords another advantage over prior art methodsand structures by preventing a problem that may arise in the fabricationsteps described in Johnson et al. Depending on etch conditions, thefirst etch, which results in the first lines of semiconductor layerstack and the first conductors, shown in FIG. 2 b, may not yieldperfectly vertical walls. Material higher in the stack is exposed toetchant longer than material lower in the stack, potentially causingsloping sides, as shown in cross-section in FIG. 4 a. The cross sectionis along plane P, shown in FIG. 2 e. For clarity, the slope isexaggerated. FIG. 4 b shows the same first lines of etched semiconductorlayer stack filled with dielectric material D. Next the secondconductors are deposited, then the second layer stack, and finally thesecond etch takes place.

Turning to FIG. 2 f, the second etch etches through a second layer ofsemiconductor layer stack, second conductors, and the first lines ofsemiconductor layer stack. When etching the first lines of semiconductorlayer stack, this etch is selective to material constituting the firstand second semiconductor layer stacks, and does not appreciably etch thedielectric material between the first lines of semiconductor layer stack(recall this dielectric material was deposited after the first etch andbefore deposition of the second conductors.) This second etch slicesthrough spaced segments of first lines of semiconductor layer stack,creating pillars. Material within the first semiconductor layer stacktrapped under overhanging dielectric material, between pillars, may notbe removed in the second etch, as shown in FIG. 4 c. The cross sectionis again along plane P, shown in FIG. 2 f. This remaining material,sometimes called a “stringer,” S, can provide an unintended electricalpath between adjacent pillars, e.g. between 45 a 1 and 45 a 2, andbetween 45 b 1 and 45 b 2 in FIG. 2 f.

Where two adjacent pillars have stringers that interfere with theirelectrical isolation from each other, the functioning of these memorycells can be compromised. Specifically, a write operation to one memorycell can undesirably affect one or both memory cells, i.e., a writedisturb condition can occur.

The present invention, by employing an improved method of fabrication,prevents formation of stringers.

Fabrication

The fabrication process of the present invention will be described firstin general terms, and then specific embodiments will be described ingreater detail.

The process typically begins on an insulating layer formed over asemiconductor substrate. First the conductors are formed. In the firststep, a thin adhesion layer, preferably of TiN, can be deposited. Abovethis a conductor material, preferably tungsten, is deposited. Tungstenhas low resistivity, so the conductor layer can be thinner than if otherconductor materials, such as TiSi₂, were used, helping to decreaseaspect ratio. The use of tungsten rather than TiSi₂ also lowers theoverall thermal budget: TiSi₂ is formed by depositing Ti on Si, thenannealing the materials to form TiSi₂. The temperature at some point ofthe processing must be at least 750 degrees C. to form the desired lowresistivity C54 TiSi₂ phase. Tungsten, on the other hand, can bedeposited at 400 to 500 degrees C. Reducing processing temperaturelimits dopant diffusion and minimizes agglomeration of materials likeTiSi₂ or CoSi₂ (which may be used in transistors underneath the memoryarray.) Dopant diffusion and silicide agglomeration are detrimental todevice performance.

Optionally, a barrier material, preferably TiN, can be deposited next.This barrier layer prevents reaction between tungsten and silicon, whichin some embodiments will be deposited in a later step. (This TiN barrierlayer is preferred but not essential. If included, it can be formedeither as the top layer in the conductor or as the bottom layer in theoverlying semiconductor element.) Next the deposited layers arepatterned and etched to form a plurality of substantially parallel firstconductors. The materials etched during this etch step are TiN andtungsten. TiN and tungsten have good etch selectivity, so etching of theTiN adhesion layer does not cause undercut of the tungsten layer. Nextthe gaps between the conductors are filled with dielectric material,preferably SiO₂, and planarized to expose the tops of the conductors,preferably by chemical mechanical polishing (CMP). The relatively shortheight of the TiN adhesion layer—tungsten conductor—(optional) TiNbarrier layer stack allows for relatively small aspect ratio fordeposition of the dielectric material in the gaps.

Next the semiconductor elements are formed. If the TiN barrier materialwas not deposited as part of the conductors, it can be deposited at thispoint, as part of the materials used to form the semiconductor elements.Above this optional TiN barrier layer, several layers of semiconductormaterial and an antifuse layer are deposited or grown. Semiconductormaterial may be doped polysilicon. Different diode-antifuseconfigurations are possible. Next the deposited semiconductor layerstack is patterned and etched to form pillar-shaped semiconductorelements. In most embodiments, the materials etched are silicon, a verythin layer of SiO₂, and a thin layer of TiN. Due to the etch chemistriesinvolved and to the thinness of the SiO₂ and TiN layers, little or noundercut occurs. Next the gaps between the semiconductor elements arefilled with dielectric material, preferably SiO₂, and planarized toexpose the tops of the semiconductor elements, preferably by CMP. Theheight of the gap to be filled with dielectric is only the height of thesemiconductor elements, so the aspect ratio remains low.

Next second conductors are formed above the semiconductor elements. Asbefore, an adhesion layer of TiN is deposited, which is followed,preferably, by a layer of tungsten, and, optionally, a barrier layer ofTiN. The deposited layers are again patterned and etched into aplurality of substantially parallel second conductors, preferablysubstantially perpendicular to the first conductors. As before, the gapsbetween the conductors are filled, preferably with SiO₂, and planarized.

The resulting structure is a bottom or first story of memory cells. Bycontinuing to form semiconductor elements and conductors, further memorycells can be built above this first story. The upper conductors of thefirst story of cells will serve as the lower conductors of an overlying,second story of cells. Ultimately the memory can be several storieshigh.

Because the gaps between conductors are filled in one deposition step,and the gaps between pillars are filled in another deposition step, theaspect ratio of the gaps to be filled is less than if gaps extendingvertically from the top of pillars to the bottom of the conductor belowwere filled in a single deposition step, as in the self-aligned process.Similarly, the shorter etches mean shorter etch times, minimizing etchundercut. The choice to etch materials with good etch selectivity in asingle patterning step for both the conductor etches and for thesemiconductor element etches also minimizes etch undercut. “Minimal etchundercut” means less than 200 angstroms of undercut measuredperpendicular to an etched wall.

What follows is a more detailed description of the present invention,including a variety of embodiments.

Formation of the memory begins with a substrate. This substrate can beany semiconducting substrate as known in the art, such as single crystalsilicon, IV-IV compounds like silicon-germanium orsilicon-germanium-carbon, III-V compounds, II-VII compounds, epitaxiallayers over such substrates, or any other semiconducting material. Thesubstrate may include integrated circuits fabricated therein.

An insulating layer is formed over the substrate. The insulating layercan be silicon oxide, silicon nitride, high-dielectric film, Si—C—O—Hfilm, or any other suitable insulating material.

The first conductors are formed over the substrate and insulator. Anadhesion layer may be included between the substrate and the conductinglayer to help the conducting layer adhere. Preferred materials for theadhesion layer are TaN, WN, TiW, sputtered tungsten, TiN, orcombinations of these materials. If the overlying conducting layer istungsten, TiN is preferred as an adhesion layer.

If such an adhesion layer is included, it can be deposited by anyprocess known in the art. Where this adhesion layer is TiN, it candeposited by depositing a TiN material, or by depositing a Ti materialand then nitriding the Ti material. The TiN can be deposited by anychemical vapor deposition (CVD) process, physical vapor deposition (PVD)process such as sputtering, or an atomic layer deposition (ALD) process.In one embodiment, the TiN material is deposited by a sputteringprocess.

The thickness of the adhesion layer can range from about 20 to about 500angstroms. In one embodiment, the thickness of the adhesion layer isabout 200 angstroms. Note that in this discussion, “thickness” willdenote vertical thickness, measured in a direction perpendicular to thesubstrate.

The next layer to be deposited is the conducting layer. If no adhesionlayer is provided, the conducting layer is the first layer deposited.This conducting layer can comprise any conducting material known in theart, including tantalum, titanium, tungsten, aluminum, copper, cobalt,or alloys thereof. TiN may be used. Where the conducting layer istungsten, it can be deposited by any CVD process or a PVD process. Inone embodiment, the tungsten is deposited by a CVD process. Thethickness of the conducting layer can depend, in part, on the desiredsheet resistance and therefore can be any thickness that provides thedesired sheet resistance. In one embodiment, the thickness of theconducting layer can range from about 200 to about 2000 angstroms. Inanother embodiment, the thickness of the conducting layer is about 1500angstroms.

If tungsten is used for the conducting layer, it is preferred to use abarrier layer between the tungsten and the semiconductor material thatwill be part of the semiconductor elements that will eventually overliethe conductors. Such a barrier layer serves to prevent reaction betweentungsten and silicon. The barrier layer may either be the top layer ofthe conductors or the bottom layer of the semiconductor elements.

If a barrier layer is to be used, and is to be formed as the top layerof the conductors, the barrier layer should be deposited after theconducting layer. Any material serving this function can be used in thebarrier layer, including WN, TaN, TiN, or combinations of thesematerials. In a preferred embodiment, TiN is used as the barrier layer.Where the barrier layer is TiN, it can be deposited in the same manneras the adhesion layer described earlier.

The thickness of the barrier layer in the finished device can be anythickness that will provide the function noted above, for example athickness of about 20 to about 500 angstroms. The final thickness of thebarrier layer is preferably about 200 angstroms. Note that planarizationof this layer will remove some material, so sacrificial material shouldbe deposited in anticipation of this. If there is no barrier layer ontop, some tungsten will be lost through CMP. However the CMP selectivityis significant between SiO₂ and tungsten, e.g., the rate at which oxideis polished is higher than the rate at which tungsten is polished. ThusSiO₂ can be removed from the top of the tungsten with confidence thatall of the SiO₂ can be removed while removing a minimal amount oftungsten.

The material used in the conducting layer and the material used in theadhesion and barrier layers, if present, should be chosen to have goodetch selectivity.

Once all the layers that will form the conductors have been deposited,the layers will be patterned and etched using any suitable masking andetching process to form substantially parallel conductors. In oneembodiment, a photoresist mask is deposited, patterned byphotolithography and the layers etched, and then the mask is removed,using standard process techniques such as “asking” in anoxygen-containing plasma, and strip of remaining polymers formed duringetch in a liquid solvent such as EKC.

The width of the conductors after etch can range from about 300 to about2500 angstroms. (In this discussion “width” will refer to the width of aline or feature measured in the plane substantially parallel to thesubstrate.) The width of the gaps between the conductors preferably issubstantially the same as the width of the conductors themselves, thoughit may be greater or less. In one embodiment, the width of theconductors is about 1500 angstroms, as is the width of the interveninggaps. As noted earlier, it becomes difficult to reliably fill gaps withdielectric material like SiO₂ when the aspect ratio of the gaps isgreater than 7:1. Thus the width of the gaps should be chosen such thatthe aspect ratio of the gaps is not greater than 7:1, and is preferablymuch smaller. Clearly the width can be reduced when the thicknesses ofthe layers comprising the conductors, and thus of the conductorsthemselves, are smaller.

It should be noted that this 7:1 limit for aspect ratio applies whenSiO₂ is used as the dielectric fill material. Alternative fillmaterials, like silicon nitride, can in fact be used for reliable fillwithout voids to fill gaps with a higher aspect ratio. SiO₂ is preferredfor several reasons, including ease of processing, low thermal budget,and low leakage as compared to silicon nitride and other dielectrics.

The width of the conductors and gap is also restricted by the selectedpitch. Pitch is the distance from one feature to the next occurrence ofthe same feature: from the center of one conductor to the center of theadjacent conductor, for example, or from the center of one semiconductorelement to the center of an adjacent semiconductor element.Semiconductor elements are to be formed above the conductors, as will bedescribed in detail below. Each semiconductor element will be formeddirectly over a conductor, so the semiconductor elements and theconductors preferably should have the same width and the same pitch. Thepitch of the conductors is limited not only by the need to achieve anaspect ratio no more than 7:1 for gaps between the conductors, but alsoto achieve the same 7:1 aspect ratio, or less, for gaps between theyet-to-be-formed overlying semiconductor elements.

Next a dielectric material is deposited over and between the conductors.The dielectric material can be any known electrically insulatingmaterial, such as silicon oxide, silicon nitride, or silicon oxynitride.In a preferred embodiment, silicon oxide is used as the insulatingmaterial. The silicon oxide can be deposited using any known process,such as CVD, or, for example, high density plasma CVD (HDPCVD).

Finally removal of the SiO₂ on top of the conductors while leaving theSiO₂ in between the conductors, a process known as planarization, isperformed. This planarization can be performed by any process known inthe art, such as CMP.

Alternatively, the conductors can be formed by a Damascene process, inwhich oxide is blanket deposited, lines are etched in the oxide, andthen the lines are filled with TiN and tungsten to create theconductors. The TiN and tungsten films on top of the original plane ofoxide are removed by any process known in the art, such as CMP, leavingTiN and tungsten wires, with dielectric material insulating the wiresfrom one another.

Next, semiconductor elements will be formed above the completedconductors. In general, a semiconductor element comprises two portionsof a diode and an antifuse. (Optionally, a barrier layer may beincluded.) Several embodiments are possible. The two portions of a diodemay be separated by an antifuse, forming an incipient diode that onlybecomes a diode when the antifuse is ruptured. Alternately, thesemiconductor element may comprise an intact diode with an antifuseabove and in series with it. In an alternate embodiment, a semiconductorelement may comprise an intact diode formed with an antifuse formedbelow and in series with it. Any of these embodiments may optionallyinclude a barrier layer as the bottom layer in the semiconductorelement.

In all of these embodiments, if a barrier layer is to be used betweenthe lower conductors and the semiconductor elements, and is to be thebottom layer of the semiconductor element rather than the top layer ofthe conductors, it will be deposited as the first layer afterplanarization of the conductors. It can be of any of the materials anddeposited in any of the manners described earlier. Its thickness, aswhen it is deposited as part of the conductors, can be, for example,about 20 to about 500 angstroms. The thickness of the barrier layer ispreferably about 200 angstroms.

Subsequent processing depends on which configuration of diode halves andantifuse is employed.

Junction Antifuse

In one group of embodiments, the antifuse is formed between two halvesof an incipient diode, which becomes a diode only when the antifuse isruptured. This configuration will be referred to as a junction antifuse.There are four most preferred embodiments of junction antifuse-typesemiconductor elements. Two are incipient P+/N− diodes (in which, forexample, heavily doped P-type silicon is on one side of the antifuse andlightly doped N-type silicon is on the other), while two are incipientN+/P− diodes (in which heavily doped N-type silicon is on one side ofthe antifuse and lightly doped P-type silicon is on the other.) Each ofthese diode types can be formed “rightside-up” or “upside-down”.“Rightside up” diodes will describe diodes in which the P+ or N+portionis deposited first, forming the bottom portion of the diode, followed bythe N− or P− portion, forming the top of the diode. “Upside down” diodesdescribes diodes in which the N− or P− portion is deposited first,forming the bottom portion of the diode, followed by the P+ or N+portion, forming the top of the diode.

The semiconductor material can be silicon, silicon-germanium,silicon-germanium-carbon, germanium, or other suitable IV-IV compounds,gallium arsenide, indium phosphide, or other suitable III-V compounds,zinc selinide, or other II-VII compounds, or a combination. Silicon isthe material used most commonly in the industry, so, for simplicity,this description will refer to the semiconductor material as silicon,but it will be understood that other materials may be substituted. Inpreferred embodiments, polysilicon is used. Silicon layers may bedeposited amorphous, then later crystallized by heat treatment, or maybe deposited as polysilicon.

To form a rightside-up P+/N− diode with junction antifuse, a layer ofheavily doped P-type silicon must be formed. This layer can be formed byany deposition and doping method known in the art. The silicon can bedeposited and then doped, but is preferably doped in situ. In apreferred embodiment, this layer can range from about 100 to about 1000angstroms, preferably 200 angstroms, and have a dopant concentration ofabout 1×10¹⁹ to about 3×10²¹ atoms/cm³, and preferably about 1×10²¹atoms/cm³.

The antifuse can be a thin layer of SiO₂. The SiO₂ can be made byoxidizing the underlying silicon layer, or silicon oxide material can bedeposited, typically using a CVD process. In one embodiment, the siliconoxide layer is grown by oxidizing the underlying silicon in O₂ plus N₂at a temperature of about 650 degrees C. for about 60 seconds. Thethickness of the SiO₂ layer can range from about 10 to about 100angstroms, and in one embodiment is about 25 angstroms.

Above the antifuse is lightly doped N-type silicon. This layer can beformed by any deposition and doping method known in the art. Thethickness of the lightly doped N-type silicon layer can range from about1000 to about 4000 angstroms, preferably about 2500 angstroms, and havea dopant concentration of about 1×10¹⁵ to about 1×10¹⁸ atoms/cm³, andpreferably 1×10¹⁶ atoms/cm³. In one embodiment, silicon is depositedwithout intentional doping, yet has defects which render it slightlyN-type.

Above this is a layer of heavily doped N-type silicon. This layer formsthe ohmic contact to the top portion of the P+/N− diode. This layer canbe formed by any deposition and doping method known in the art. Thethickness of the heavily doped N-type silicon can range from about 100to about 2000 angstroms, preferably about 1000 angstroms. Note this isthe thickness as-deposited. If this layer is subject to laterplanarization, as in most embodiments, it will be thinner in thefinished device. This layer has a dopant concentration of about 1×10¹⁹to about 1×10²¹ atoms/cm³, preferably 5×10²⁰ atoms/cm³.

Using conventional equipment and techniques, when doped silicon isdeposited in a furnace, doped silicon is deposited not only on the wafersurfaces, but also on every other surface in the furnace. If the nextdeposition in the same furnace is of undoped silicon, or silicon of theopposite conductivity type, outgassing of the dopant from silicondeposited in the previous deposition can compromise doping quality. Thisis known variously as autodoping or the memory effect. To prevent this,the semiconductor element can be “capped” by an undoped layer of silicondeposited to a thickness of at least about 200 angstroms. This undopedlayer of silicon covers and seals the previously deposited doped siliconcoating surfaces in the furnace, protecting the next deposited layerfrom outgassed dopant. This technique is described in Herner U.S. patentapplication Ser. No. 09/859,282, filed May 17, 2001, now U.S. Pat. No.6,635,556, and hereby incorporated by reference. The undoped “cap” willbe removed by a subsequent planarization step and therefore will notbecome part of the finished device. This technique can be used at anypoint when sequential depositions of different conductivity types are tobe performed in the same furnace, and when future processing will removethe undoped cap.

For an upside-down P+/N− diode with a junction antifuse, the same layersare formed with the same dimensions and in same way, but in a differentorder: first the heavily doped N-type silicon layer, which forms theohmic contact to the diode then the lightly doped N-type silicon layer,then the antifuse, then the heavily doped P-type silicon layer.

The rightside-up and upside-down N+/P− diodes with junction antifuse usethe same layers as the P+/N− diodes, though with the conductivity typeof each doped silicon layer reversed: A rightside-up N+/P− diode, fromthe bottom up, includes heavily doped N-type silicon, an antifuse,lightly doped P-type silicon, and heavily doped P-type silicon. Theheavily doped P-type silicon forms the ohmic contact to the top portionof the diode. An upside-down N+/P− diode, from the bottom up, includesheavily doped P-type silicon, which forms the ohmic contact to thebottom of the diode, lightly doped P-type silicon, an antifuse, andheavily doped N-type silicon. The deposition and doping methods are asknown in the fields, and the thicknesses of the layers are as describedabove for the corresponding layer with conductivity types reversed.

Top Antifuse

In another group of semiconductor element embodiments, the antifuse isformed on top of a diode. This configuration will be referred to as atop antifuse. As with the junction antifuse group of embodiments, thediode can be either a P+/N− or an N+/P− diode, and can be builtrightside-up or upside-down. For preferred top antifuse embodiments, theantifuse is grown after the diode has been etched, filled, andplanarized.

A top antifuse-type rightside-up P+/N− diode will comprise, from thebottom up, the following layers: heavily doped P-type silicon, lightlydoped N-type silicon, heavily doped N-type silicon (which forms theohmic contact to the top of the P+/N− diode), and an antifuse. The samediode, upside down, will comprise, from the bottom up: heavily dopedN-type silicon, which forms the ohmic contact to the bottom of the P+/N−diode, lightly doped N-type silicon, heavily doped P-type silicon, andan antifuse.

A top antifuse-type rightside-up N+/P− diode will comprise, from thebottom up: heavily doped N-type silicon, lightly doped P-type silicon,heavily doped P-type silicon, which forms the ohmic contact to the topof the diode, and an antifuse. The same diode, upside-down, willcomprise, from the bottom up: heavily doped P-type silicon, which formsthe ohmic contact to the bottom of the diode, lightly doped P-typesilicon, heavily doped N-type silicon, and an antifuse.

In the junction antifuse embodiments above and the bottom antifuseembodiments described below, all of these layers are deposited (orgrown), then patterned and etched, the gaps filled with dielectric, andsemiconductor elements and intervening dielectric fill planarized. Mosttop antifuse embodiments deviate from that pattern for the formation ofthe antifuse.

A very thin antifuse layer formed on top of the semiconductor elementwould be highly vulnerable to inadvertent damage or removal if subjectedto planarization. For preferred top antifuse embodiments, the antifuseis formed after planarization. The doped silicon layers are depositedand doped using any process known in the art (using the undoped cap ifdesired), then patterned, etched, filled, and planarized to exposeheavily doped silicon at the top of the semiconductor element. Afterplanarization is complete, the exposed silicon is oxidized and a SiO₂antifuse grown on top of it.

An advantage of the top antifuse embodiments is reduced processing time.In the junction antifuse embodiments, to deposit the layers that willform the diode portions and the antifuse, first silicon is deposited,then the antifuse is formed, either through deposition of SiO₂ or byoxidation of the top of the underlying silicon, and then more silicon isdeposited. After the first deposition of silicon, the wafers must beunloaded and moved to another tool (for rapid thermal anneal, forexample), to grow the antifuse. Then the wafers must be moved back tothe furnace for the next silicon deposition. In the top antifuseembodiments, on the other hand, only a single deposition of silicon isrequired, reducing processing time and cost, and reducing exposure tocontaminants cause by extra handling.

Bottom Antifuse

In another group of embodiments, the diode is formed above the antifuse.This configuration will be referred to as a bottom antifuse. As with thejunction antifuse group of embodiments, the diode can be either a P+/N−or an N+/P− diode, and can be built rightside-up or upside-down.Deposition of the silicon layers, and their dopant levels andthicknesses, can be as described in the top antifuse embodiments.

If a barrier layer of TiN is used, either as the top layer of theconductor or as the bottom layer of the semiconductor element, thesebottom antifuse embodiments present some challenges. If SiO₂ is used asthe antifuse, a SiO₂ layer directly on top of TiN cannot be grownthrough oxidation, as it can when being formed on top of silicon.Instead it is deposited directly as SiO₂. It is difficult to deposit athin stoichiometric layer of SiO₂ on top of TiN. These embodiments arethus less preferred. Clearly, other dielectric materials could be usedinstead.

Pattern, Etch, Fill, and Planarize

When the layers that will form the optional bottom barrier layer, thediode portions and the antifuse are deposited (omitting the antifuse,which will be grown later, in the top antifuse embodiments), the layersshould be patterned and etched to form semiconductor elements. Thesemiconductor elements should have the same pitch and the same width asthe conductors below, such that each semiconductor element is formed ontop of a conductor.

With perfect alignment, the center of a semiconductor element should belocated directly over the center of the conductor below it, as in FIG. 5a. A significant amount of misalignment can be tolerated, however, as inFIG. 5 b. As long as a semiconductor element isn't 100 percentmisaligned, bridging adjacent conductors and forming an electricalcontact with both of them, as in FIG. 5 c, the resulting device canfunction successfully with substantial misalignment. The bulk of theresistance in the circuit described, namely a programmed diode/antifusein contact with conductors, should come from the diode, which has aresistivity in the thousands of ohms due to the use of lightly dopedsilicon. In contrast the contact resistance between the tungsten/TiNwire and heavily doped silicon is less than 100 ohms. Therefore, even ifmisalignment between the wiring and semiconductor element results inonly 10 percent of the semiconductor area being in contact with thewiring either above or below, the resistance will not be substantiallydifferent than perfectly aligned layers in which 100 percent of thecross section of the semiconductor element is in contact with thewiring.

Referring to FIG. 6 a, underlying conductors C1 extend in a firstdirection D1. If underlying conductors C1 and overlying semiconductorelements S1 are to align, then clearly the pitch P1 of the semiconductorelements S1 in a second direction D2 (preferably substantiallyperpendicular to the first direction D1) must be the same as the pitchP1 of the underlying conductors C1. The pitch P2 of the semiconductorelements S1 in the first direction D1, however, is not constrained bythe pitch P1 of the underlying conductors C1.

Later in the process, as shown in FIG. 6B, overlying conductors C2 willbe formed over the semiconductor elements. Overlying conductors C2extend in the second direction, D2. The pitch P2 of the semiconductorelements S1 in the first direction D1 should be chosen to align with theoverlying conductors to be formed above, and thus should be at a pitchP2 allowing alignment with their intended pitch P2 and orientation. Aswith the underlying conductors, substantial misalignment between thesemiconductor elements and the overlying conductors can be tolerated.

The semiconductor elements can be formed using any suitable masking andetching process. For example, a photoresist mask can be deposited,patterned using photolithography and etched, and then thephotolithography mask removed. Alternately, a hard mask of some othermaterial, for example SiO₂, can be formed on top of the semiconductorlayer stack, with bottom antireflective coating (BARC) on top, thenpatterned and etched. Similarly, dielectric antireflective coating(DARC) can be used as a hard mask. The resulting structure at this stageof the process is shown in FIG. 6A.

For reasons explained more fully below, rectangular features formed withfeature size in both dimensions less than about 2500 angstroms usingstandard photomasking techniques tend to be substantially cylindrical,regardless of the shape of the mask. The semiconductor elements afteretch thus will be substantially cylindrical, with a diameter rangingfrom about 300 to about 2500 angstroms. The width of the gaps betweenthe semiconductor elements preferably is substantially the same as thediameter of the semiconductor elements themselves, though it may begreater or less. In one embodiment, the diameter of the semiconductorelements is about 1500 angstroms, as is the width of the interveninggaps at their narrowest point.

As noted earlier, it becomes difficult to fill gaps with dielectricmaterial such as SiO₂ when the aspect ratio of the gaps is greater than7:1. Thus the width of the gaps should be chosen such that the aspectratio of the gaps is not greater than 7:1. Clearly the width can bereduced when the thicknesses of the layers comprising the semiconductorelements, and thus of the semiconductor elements themselves, aresmaller.

Next a dielectric material is deposited over and in between thesemiconductor elements, filling the gaps between them. The dielectricmaterial can be any known electrically insulating material, such assilicon oxide, silicon nitride, or silicon oxynitride. In a preferredembodiment, SiO₂ is used as the insulating material. The SiO₂ can bedeposited using any known process, such as CVD, or, for example, HDPCVD.

Planarization is then performed to remove the dielectric material on topof the semiconductor elements and expose their top surfaces, whileleaving the dielectric in between them. This planarization can beperformed by any process known in the art, such as CMP. In preferred topantifuse embodiments, a SiO₂ antifuse layer is then grown on top of theexposed silicon after CMP.

Overlying conductors can be formed in the same manner as the underlyingconductors. The resulting structure is a bottom or first story of memorycells. By continuing to form semiconductor elements and conductors,further memory cells can be built above this first story. The upperconductors of the lower story of cells will serve as the lowerconductors of an overlying, second story of cells. Ultimately the memorycan be several stories high. In a preferred embodiment, the memory cancontain from two to twelve stories. In another preferred embodiment, thememory contains eight stories.

One advantage afforded by the current invention is that in allembodiments the top layer of the semiconductor element whenplanarization is performed on it (and on the intervening dielectricfill) is a heavily doped layer. CMP (or another planarizing method) willreduce the thickness of the layer on which it is performed. Thisreduction in thickness can be difficult to control, and may vary acrossa wafer. The thickness of the lightly doped layer in a diode is criticalto diode properties like leakage and reverse stress failure. It isdesirable for all devices to have the same, or very nearly the samethickness of the lightly doped layer. Performing planarization on thislayer, which results in a thickness that can vary greatly not only fromwafer-to-wafer, but also within the wafer, makes for a less robustprocess. The thickness of the heavily doped layers, on the other hand,is much less crucial to device performance. Their thickness can vary toa much larger degree while not affecting the device performance greatly.Planarizing on these layers is far less likely to compromise devicereliability.

Density

The feature size of the three dimensional memory cell of the presentinvention, and thus the density of an array composed of such cells, islimited by the thickness (height) of the conductors and of thesemiconductor elements. Because of the 7:1 aspect ratio limit forreliable SiO₂ gap fill, the gap between features can be no smaller thanone-seventh of the height of the features. The semiconductor elementsare generally thicker than the conductors, and thus it is theirthickness that limits the feature size of the memory cell. Recall thesemiconductor element material is deposited, then patterned, etched, andthe gaps between the elements filled with dielectric material. Thus, theaspect ratio immediately before dielectric fill is the relevant measureof aspect ratio. After dielectric gap fill, planarizing will remove somesemiconductor material at the top of the semiconductor element, inaddition to the dielectric. The height of the semiconductor element inthe finished device, then, is less than its deposited height.

The height of the semiconductor element is the combined height of thebarrier layer (if present), the semiconductor layers, and the antifuse.In the junction antifuse rightside-up P+/N− diode embodiment with a TiNbarrier layer, for example, in one preferred embodiment, the heights ofthese layers are: 200 angstroms (TiN), 200 angstroms (heavily dopedP-type silicon), 25 angstroms (antifuse), 2900 angstroms (lightly-dopedN-type silicon), and 1000 angstroms (heavily doped N-type silicon andundoped cap.) The total of these thicknesses, the height of thesemiconductor element at the time of gap fill, is 4325 angstroms. At a7:1 aspect ratio, the size of the gap between the semiconductor elementscan be about 600 angstroms.

If the smallest preferred thickness for each layer is used instead,those values are 20 angstroms (TiN), 200 angstroms (heavily doped P-typesilicon), 10 angstroms (antifuse), 1000 angstroms (lightly-doped N-typesilicon), and 1000 angstroms (heavily doped N-type silicon and undopedcap.) The total is 2230 angstroms, which, at 7:1 aspect ratio, allowsfor a feature size of about 300 angstroms.

Larger thicknesses can also be used: 500 angstroms (TiN), 1000 angstroms(heavily doped P-type silicon), 100 angstroms (antifuse), 4000 angstroms(lightly-doped N-type silicon), and 2000 angstroms (heavily doped N-typesilicon and undoped cap.) Using these thicknesses, the total height is7600, for a feature size of about 1100 angstroms. Clearly, still largerthicknesses and feature sizes are possible as well.

Decreasing feature size allows for a substantial reduction in areadensity; i.e., memory cells formed on or over an area of substrate. Forexample, in memory devices like those described in Johnson et al., thearea of a memory cell can be represented as 4F², where F is the featuresize. Because stories of memory are stacked vertically, the area densityof memory devices (cells per area) is n/(4F²), where n is the number ofmemory stories. At a feature size of 0.03 micron, with twelve memorystories, then, an area density of 3.3×10⁹ cells/mm² can be achieved. Ata feature size of 0.06 micron, with eight memory stories, an areadensity of 5.6×10⁹ cells/mm² can be achieved. At a feature size of 0.14micron, with eight memory stories, an area density of 1.0×10⁹ cells/mm²can be achieved. At a feature size of 0.14 micron, with four memorystories, an area density of 5.0×10⁷ cells/mm² can be achieved.

It is also useful to consider cubic density of memory, or memory cellsper volume. In the present invention, the volume of a cell is z4F²,where z is height of the memory cell, assuming (for simplicity) that noinsulation is needed between layers. Inverting this value (1/(z4F²)yields the cubic density.

The final height of the semiconductor element and barrier layer can beabout 1430 angstroms or greater and the height of the conductor can beabout 220 angstroms or greater. Recall that the height of thesemiconductor element in a finished device is less than its as-depositedheight, since material is removed by planarization. A semiconductorelement and barrier layer with an as-deposited height of 2230 angstroms,after deposition of fill material between semiconductor elements, willbe planarized, which can reduce its completed height to, for example,about 1430 angstroms.

The height of any individual cell with these dimensions, then, can beabout 1430+220=1650 angstroms or greater. Thus, with the 0.165 micronheight of a memory cell and a feature size of 0.03 micron the cubicdensity of these devices can be calculated to be about 1.7×10¹² devices(or bits)/mm³.

A semiconductor element and barrier layer with an as-deposited height ofabout 0.43 micron, could, after planarizing, have a finished height of,for example, 0.35 micron. The conductor thickness could be, for example,0.15 micron, yielding a cell height of about 0.50 micron. With a featuresize of 0.06 micron (achievable with an as-deposited height of 0.43micron, as described above), a cubic density can be calculated at about1.4×10¹¹ cells/mm³.

A semiconductor element and barrier layer with an as-deposited height ofabout 0.76 micron, could, after planarizing, have a finished height of,for example, 0.68 micron. The finished conductor thickness could be, forexample, 0.18 micron, yielding a cell height of about 0.86 micron. Witha feature size of 0.11 micron (achievable with an as-deposited height of0.76 micron), a cubic density can be calculated at about 2.4×10¹⁰cells/mm³. These area and cubic densities represent a significantimprovement over other three dimensional memories.

It has been noted that the semiconductor elements will have asubstantially cylindrical shape. As feature size decreases insemiconductor processing, current photolithography techniques tend toround any sharp corners on features. It is believed that this roundingoccurs because photons used in the process diffract around the featuresin the plate used for patterning, resulting in rounded features beingprinted in the photoresist mask. Thus, the semiconductor element that isetched with this photoresist mask with rounded features will typicallyhave no sharp corners.

A “substantially cylindrical” element is one with a cross section whichis roughly circular; more specifically, a cross section in which noportion of the perimeter is a straight edge for a length longer thanfifty percent of the longest dimension measured through the centroid ofthe cross-sectional area. Clearly, a straight edge will not be“straight” to a molecular level, and may have minute irregularities;what is relevant is the degree of rounding. Examples appear in FIG. 7.

The substantially cylindrical shape provides one advantage to the memorydevices: reduced current leakage. Semiconductor elements having sharpcorners often have current leakage at the corners. The current leakageis also proportional to the cross-sectional area of the semiconductorelement, so a substantially cylindrical shape provides the smallest areafor a given feature size.

It will be apparent to one skilled in the art, however, that thesubstantially cylindrical shape of the semiconductor elements is anincidental result of using conventional photolithographic techniques toproduce very small features, and, while advantageous, some aspects ofthe invention could be practiced with semiconductor elements of adifferent shape.

Contact Formation

In monolithic three dimensional memories of the type created accordingto the present invention, vertical interconnects, termed zias (analogousto vias in conventional two dimensional memories), may be used toconnect different stories of memory. Specifically, zias are electricallycoupled to active devices on different stories. An “active device” isany device that has asymmetric current versus voltage characteristics.Examples of active devices include diodes and transistors. An activedevice is contrasted with a passive device, which does not controlvoltage or current. Examples of passive devices include resistors,capacitors, and inductors. The memory cells of the present inventioninclude diodes, and thus are active devices.

Prior art zia formation in monolithic three dimensional memories isdescribed in Cleeves et al. U.S. patent application Ser. No. 09/746,341,filed Dec. 22, 2000, now U.S. Pat. No. 6,664,639, and herebyincorporated by reference. The materials and methods used by the presentinvention, particularly of the conductors, simplify formation of zias.

Zia formation according to the present invention takes two primaryforms, one for junction antifuse and bottom antifuse embodiments, andanother for top antifuse embodiments. Each will be described in turn.

Junction and Bottom Antifuse Zias

Turning to FIG. 8, the illustration shows an array of conductors andsemiconductor elements. The bottom conductors, extending in theX-direction (in this illustration coming out of the page) are labeledX₁, the ones above, extending in the Y direction, are Y₂, the onesabove, extending in the X direction, are X₃, etc. As has been described,there are semiconductor elements sandwiched between each set ofconductors. The array is shown when the Y₆ conductors, along with ziasconnecting them to the Y₄ and Y₂ conductors, are about to be formed.

Note that as in Cleeves et al., in this drawing the lengths of the Y₂and Y₄ conductors are staggered to create “landing pads” that areaccessible from upper memory layers.

To form zias for junction antifuse and bottom antifuse embodiments,first a pattern and etch is done to remove the dielectric materialbetween the conductors where the zia is to formed, which may be anyinsulating material, preferably SiO₂. This etch forms a contact void, ahole where the zia is to be formed. In the preferred embodimentillustrated here, the conducting layers are tungsten, and a TiN barrierlayer between the tungsten of each conductor and the semiconductingmaterial of its overlying semiconductor element is formed as the bottomlayer of the semiconductor element. The top of each conductor, then, isof tungsten. (It will be understood that other embodiments using othermaterials can be employed. This preferred embodiment is selected tosimplify explanation.)

There are chemistries which produce high etch selectivities between SiO₂and tungsten and between SiO₂ and TiN, allowing all the unwanted SiO₂ tobe successfully etched without substantial etch damage to the exposedconductors Y₂ and Y₄.

Next the TiN adhesion layer that normally forms the bottom of the Y₆conductors being formed is deposited, simultaneously creating theadhesion layer for the Y₆ conductors and lining the etched contact void.The TiN can be deposited by a method that creates a substantiallyconformal film, such as CVD. Alternatively, a method such as ionizedmetal plasma PVD (IMP-PVD) which preferentially deposits TiN onhorizontal features, such as landing pads, can be used. Finally thetungsten conducting layer is deposited, completing deposition of theconducting layer for the Y₆ conductors and filling the zia. One sidewallof the zia has a stair-step profile. No special deposition steps ormaterials are required to form the zia; its layers are formed at thesame time, by the same depositions, as are the layers that will becomethe Y₆ conductors. For two structures to be formed “by the samedeposition” means in the same deposition chamber, of the same depositedmaterial, without stopping and restarting the deposition process. TheTiN in the contact and in the Y₆ conductors is formed by the samedeposition. Similarly, the tungsten in the contact and in the Y₆conductors is formed by the same deposition. The low resistivity oftungsten means zias can be long and retain good conductivity. The Y₆conductors are then patterned, etched, filled, and planarized as usual.

Top Antifuse Zias

A different process can advantageously be used to create zias for topantifuse embodiments. The zia formation process just described forjunction and bottom antifuse embodiments started with a pattern and etchstep to etch the SiO₂ where the zia is to be formed, creating thecontact void. This pattern and etch step could involve, for example,patterning photoresist on top of the areas not be etched, etching, thenremoving photoresist. If such a process were performed in top antifuseembodiments, however, the process of applying and removing photoresistcould damage the antifuse immediately beneath it. Damage to the antifusewill adversely affect function of the memory cell.

The antifuse in this context is a critical film, where “critical film”describes a layer whose quality and thickness has a critical influenceon device performance.

Zia formation for top antifuse embodiments will be described starting atthe point illustrated in FIG. 8, when the Y₆ conductors, along with ziasconnecting them to the Y₄ and Y₂ conductors, are about to be formed.

To avoid damage to the fragile antifuse that could be caused by removingphotoresist, a hard mask of TiN is deposited instead. This TiN layer canbe deposited by any method that will not harm the antifuse beneath it(non-biased PVD, for example) and can be from 100 to 1000 angstromsthick, preferably 300 angstroms thick. This TiN layer will become thefirst part of the adhesion layer at the bottom of the Y₆ conductor,still to be formed.

In this embodiment, the TiN at the bottom of a conductor, in addition toacting as an adhesion layer, also acts as an electrode adjacent theantifuse. Any conductive material deposited immediately above theantifuse acts as an electrode. The TiN layer just deposited, then, isthe first part of an electrode adjacent the antifuse.

To create the contact void where the zia is to be formed, the TiN hardmask and the dielectric between conductors, preferably SiO₂, need to beetched. This can be done using any pattern and etch technique. In oneembodiment, a TiN etch can be performed in one chamber, then a SiO₂ etchcan be performed in a second chamber. In another, TiN and SiO₂ areetched in a single chamber.

The resulting structure is shown in FIG. 9. The TiN hard mask 90 remainsafter the pattern and etch. A second TiN film can be deposited by anyknown method that will produce a conformal film; it will simultaneouslyline the volume etched for the zia and, together with the underlying TiNhard mask, form the bottom of the conductor. This second TiN film is thesecond part of an electrode adjacent the antifuse. Finally the tungstenconducting layer is deposited, completing deposition for the Y₆conductors and formation of the zia. One sidewall of the zia has astair-step profile. The Y₆ conductors are then patterned, etched,filled, and planarized as usual.

Alternately, for junction, top, or bottom antifuse, the conductors neednot be staggered to form the landing pads shown in FIG. 8, and moreconventional contacts can be formed instead, without a sidewall having astair-step profile.

The current invention provides a method for creating a monolithic threedimensional memory array. The memory cells can be electrically connectedin the embodiments described in Johnson et al. or Knall et al., butother arrangements can be envisaged as well.

Example

A detailed description of one preferred embodiment of the presentinvention is provided below. Due to its cylindrical shape, in thisdescription the semiconductor element is referred to as a “beer can.”The bottom story of conductors or “wiring” will be referred to as X1,the one above it as Y2, the one above it as X3, etc. The bottom story ofbeer cans will be referred to as beer can 1, the one above as beer can2, etc. This example describes creating a memory array with two storiesof memory; memory arrays with more or fewer stories can be created.

Before creation of the monolithic three dimensional memory above thesubstrate begins, supporting circuitry, such as complementary metaloxide semiconductor (CMOS) transistors, may be created in the wafer. Thesteps detailed below begin with wafers processed though completion ofCMOS transistors, and referred to as “the front end.” The final step isthe routing layer CMP. The routing layer is the conductive wiringconnecting the CMOS transistors below, for example, to the memory cellsabove.

In the following description, the finished memory array includes N⁺, P⁺and undoped polysilicon. Through all stages of deposition,photolithography, etch, and polish, all of these layers are referred toas polysilicon. In some embodiments, though, only the P⁺ silicon isactually deposited as polysilicon, while the N⁺ and undoped silicon aredeposited as amorphous silicon and are crystallized into polysilicon bya final anneal, which also serves to activate dopants in the silicon.

Step 1: 200 Å TiN Deposition:

No preclean, or removal of native oxide, is performed prior to metaldeposition. An appropriate deposition tool is the Applied MaterialsEndura, with a throughput of about 80 wafers per hour (WPH). Recipe: 200Å (angstroms) IMP TiN (IMP is biased sputtering which produces moreconformal films than non-biased sputtering). No bias is needed becauseno step coverage is required.

Step 2. 1500 Å Tungsten Deposition:

The tool used is the Novellus Concept One (throughput about 45 WPH).Recipe is as follows: Temperature is 445° C., pressure is 40 mTorr.Nucleation Step: 15 sccm SiH₄, 40 sccm WF₆, 1000 sccm Ar, 10000 sccm H₂,5.5 sec. Via fill (per stage): 40 sccm WF₆, 9000 sccm Ar, 10000 sccm H₂,6 sec. There are five stages total: one for nucleation and four for viafill, so via fill step is repeated four times.

Note: Low stress W is required. Stress: σ=1.18 E10 dynes/cm²′ SheetResistance: 1500 Å W=1.3 Ω/square.

Step 3: First Wiring Layer (X1) Photolithography:

Mask Dimensions: 0.15 μm line+0.17 μm space. Resist Coater: DNS. Scannerused is ASML /500 (40 WPH). 600 Å BARC—Shipley AR2. 4620 Å Shipley UV135 Resist. PEB/soft bake temp=130° C./130° C. Exposure: 28 mJ/cm²(annular). Focus: 0.0 μm. DI CD Spec: Line CD: 0.16±0.02 μm. Dense toIsolated Bias: 0.04 μm. Overlay Spec: ±60 nm.

If using an ASM 5500/500 DUV scanner, use an N.A. setting of 0.63(maximum available). Use annular illumination with an inner sigmasetting of 0.50 and an outer sigma of 0.80. To accomplish 0.15 mmresolution with this tool, a k₁ value of 0.37 is necessary. This is atthe limit of the /500's capability. Results will be much improved with amore capable photolithography tool. The severe proximity effects createdby using the /500 are dealt with by a mask level adjustment to isolatedlines. An extra 0.04 mm can be added to any side of a line that faces aspace greater than 0.25 mm. This correction is process andphotolithography tool specific. Because of the heavy use of chemicalmechanical polishing (CMP) and opaque thin films in the back end of theprocess, most alignment and overlay marks below the top surface arefilled in and invisible. ASML SPM (scribe line) marks are used forlayer-to-layer alignment. Achieving the necessary step height for analignment signal depends on the differential polishing rate between thepatterned and fill materials.

Note that variation in CMP can directly affect alignment. As long as theCMP process is consistent and reproducible, good overlay can bemaintained. If the process shifts, or cannot be controlled, a change inoverlay will be seen. Typically, CMP induces rotational, and sometimesscaling, misalignment. Step 4: First Wiring Layer (X1) Etch:

Step 4a: Etch 1500 Å W and 200 Å TiN:

Etch tool used is LAM 9600 (35 WPH). Recipe: (Chuck Temp=45° C.). BARC:12 mT/400 TCP/60 BP/50 BCl₃/25″. W: 12 mT/600 TCP/100 BP/60 SF₆/11 N₂/15BCl₃/Ept (˜25″) +25% OE. TiN: 8 mT/500 TCP/80 BP/30 Cl₂/50 BCl₃/20″. TheW etch rate is about 3600 Å/min.

Resist/BARC remaining after etch is about 500 Å. Oxide Gouge=˜350 Å(dense); −650 Å (isolated). Wall angle is 88-90°.

Step 4b: Plasma Strip:

Tool used is Gasonics (an alternative is 9600 Strip). Recipe: N2/O2 ash,30 s, 270° C.

Step 4c: Post Strip Clean:

Tool used is Semitool. Recipe: EKC 265 Clean, 65° C., 10 min. Line CD is0.15±0.02 μm. Dense to Isolated Bias is 25 nm. Dense lines shrink atetch by ˜15 nm while isolated lines grow by 10 nm.

Need to clear any large unstepped areas to avoid tungsten peeling.

Step 5: X1 (First Wiring Layer) Fill:

2500 Å HDP oxide deposition is performed. No preclean is required.Deposition tool can be Novellus Speed, or AMAT HDP. Silane oxidedeposition conditions correspond to an etch to deposition (E/D) ratio ofabout 0.25 in Novellus; equivalent AMAT HDP D/S ratio=3.2.

Gap is 0.17 μm tall and 0.17 μm wide, for an aspect ratio of 1:1. AMATHDP is recommended to prevent alignment mark distortions.

Step 6: X1 CMP:

To perform CMP on HDP oxide, use Westech, with main polish rate about2700 Å/min. AMAT Mirra can also be used. Ontrak DSS-200 with 1% NH₄OHthrough the brush (no HF).

Consumables used for main polish are Cabot SC-1, IC1000/SubaIV, and SP1CVD diamond conditioner disk. Consumables used for buff: Politexregular.

Recipe: Remove equivalent to 1600 Å on blanket TEOS wafer. 100 Å oxideremoval occurs in final platen slurry buff.

There is minimal W loss, some rounding of corners, smoothing of grains.Politex platen-3 buff with slurry removes approximately 100 Å fromblanket wafer after main polish. Oxide dishing occurs between W lines ofabout 200 Å to 300 Å. Center to edge variation (oxide loss) is 200 to300 Å.

Step 7: Diode 0 (Beer can 1) TiN Deposition:

To perform 200 Å TiN deposition, no preclean is needed. The tool used isAMAT Endura (80 WPH). Recipe is IMP TiN with bias; MOCVD or PVD TiN canbe used. This layer is a barrier layer between W and polysilicon. It canbe thinner, and is required to minimize leakage.

Step 8: Diode 0(Beer can 1) Polysilicon Deposition:

Deposit 200 Å P⁺ polysilicon, 2900 Å undoped polysilicon, 800 Å N⁺polysilicon, and 200 Å undoped polysilicon. Tool used is ASML SVG.Recipe is 540° C., 400 mTorr. Remaining recipe conditions are shown inTable 1.

TABLE 1 1.5% 1.5% Step Time Silane Helium BCl₃ PH₃ 200 Å 1e21 P⁺ 5:00500 700 100 — Si sccm sccm sccm 2900 Å undoped 2:22:40 500 — — — Si sccm800 Å 5e20 N⁺ 1:08:00 500 380 — 40 Si sccm sccm sccm 200 Å undoped 10:45500 — — — Si sccm

Dopants and concentration for in-situ doping: For P⁺ dopant, use boronat 1.0×10²¹ per cm³; for N⁺ dopant, use phosphorous at 5.0×10²⁰ per cm³.Thickness variation within a wafer should be less than 2% (3 sigma);across a load, less than 3% (3 sigma); and from load to load, less than2% (3 sigma).

600 Å of the N⁺ polysilicon thickness and the undoped polysilicon can besacrificial for CMP polishing. At least 200 Å of N⁺ polysilicon isrequired for ohmic contact to subsequent TiN/W. Undoped polysilicondeposited as the last deposition eliminates autodoping, and can beremoved in subsequent CMP step.

Alternatively, ion implantation can be used instead of in situ dopingfor the N⁺ layer. Such implantation would be done after the beer canCMP.

Step 9: Diode 0 (Beer can 1) Oxide Hard Mask Deposition:

Deposit 400 Å of oxide hard mask using a Novellus Oxide tool.

Hard mask is low temperature silane oxide. This hard mask is required ifASML/500 photolithography tool is used, but may not be necessary if abetter tool is used. Hard mask improves silicon thickness uniformityafter CMP, because hard mask deposition is more uniform than filldeposition.

Step 10: Diode 0 (Beer can 1) Photolithography:

Use DNS resist coater and ASML/500 scanner or ASML/700 scanner. Deposit900 Å BARC (or, alternately, DARC) and 4270 Å UV 135 resist. Perform PEBand soft bake at 130° C./130° C. Exposure is 20 mJ/cm². Focus: 0.0 μm.

The beer can ideal CD is 0.15±0.02 μm. Overlay specification is ±60 nm.

If the beer can mask is to be printed using ASML/500, it should be sizedup to 0.17 μm and printed with about a 20 nm positive bias. If an ASML/700 scanner or better will be available, the mask may be printed withbetter fidelity.

Other problem associated with using /500 for 0.15 μm posts are: lowresist thickness (about 3500 Å resist after develop) and poor profilewarranting a hard mask at etch.

Misalignment can be tolerated. At nominal dimensions for beer cans and Wconductors, contact area varies with misalignment as shown in Table 2:

TABLE 2 Linear Misalignment Contacted Area +/− 0 nm  100% +/− 50 nm  70%+/− 75 nm  50%  +/− 100 nm  30%  +/− 125 nm  17%

In the case of the wiring layers: X1, Y2, . . . , X9, the polishing ratefor tungsten is near zero so the CMP selectivity of tungsten to oxide ishigh. This makes it relatively easy to make a useable alignment mark.ASML specifies a target step height of 1200 Å. Experience has shown thatfor this process, any step height greater than 200 Å is sufficient toget good alignment. Between 40 Å and 200 Å, alignment may still work,but it is not reliable. Values greater than 200 Å are typically achievedfor the wiring layers.

Step 11: Diode 0 (Beer can 1) Etch:

Etch the following layers: 900 Å BARC, 400 Å Oxide, 200 Å undopedpolysilicon, 800 Å N⁺ polysilicon, 2900 Å undoped polysilicon, 200 Å P⁺polysilicon and 200 Å TiN. The etch tool used is 9400 DFM (44 wph for 4chamber tool).

The following etch recipe is used (cathode Temp: 60° C.): For BARC, 5mT/250 TCP/−200 BV/100 CF₄/Ept. For the hard mask, 5 mT/250 TCP/−200BV/100 CF₄/20″. Polysilicon main etch (ME): 10 mT/350 TCP/90 BP/40Cl₂/150 HBr/15 He O₂/Ept(˜100 s)+5% OE. Polysilicon over etch (OE): 80mT/400 TCP/60 BP/100 HBr/200 He/19 He O₂/45″. TiN: 5 mT/250 TCP/120BP/10 Cl₂/50 HBr/50 He/30″.

To perform the plasma resist strip, use the Novellus Iridia. The recipeis ˜2.5% CF₄ in O₂, 1375 W MW, 50 W RF, 40° C., 105 s. 100% O₂, 0 W MW,420 W RF, 40° C., 60 s.

The solvent clean tool is Semitool, and the recipe is EKC 265 Clean—10minutes. The beer can CD is 0.21±0.03 μm. The CD is higher due to maskbiasing. The ideal can CD is 0.17±0.02 μm. CD Bias: ˜20 nm. relative tophotolithography.

Gouge into W during OE is <100 Å, and gouge into oxide during over etchis <100 Å.

Polysilicon OE step is selective to TiN. CF4 containing ash with bias inIridia helps clean up polymer without HF dip.

Step 12: Diode 0 (Beer can 1) Fill:

For 4000 Å HDP Oxide Deposition (3 chambers; 60 WPH), use Novellus Speedor AMAT HDP. In the case of Novellus deposition, the E/D ratio=0.25;equivalent AMAT HDP D/S ratio=3.2.

Thickness should be 4100±200 Å. AMAT HDP is recommended since NovellusHDP fill causes asymmetry and thereby affecting alignment at photo.

Step 13: Diode 0 (Beer can 1) CMP:

To CMP the HDP oxide, tools and consumables are the same as for theconductor polish in Step 6. Oxide removal target is 700 Å. Oxide hardmask must be removed from beer can structures. It is acceptable to leaveundoped polysilicon on beer cans after polish. It is acceptable to leaveunpolished oxide on other structures. After polish, the beer can musthave a minimum of 200 Å of P⁺ polysilicon remaining, such that totalstack height is 3100 to 4300 Å after polish.

Polish times are very short for 700 Å target. Ramp-up plus buff stepsremove approximately 250 Å. Main polish step is typically 9 to 10seconds. The buff step, if used removes approximately 100 Å after mainpolish. Center to edge oxide loss variation is about 100 to 200 Å.

Step 14: Beer Can 1 Antifuse Growth:

18 Å of antifuse oxide must be grown. Perform preclean first: 100:1 HFdip; 45 s. Antifuse oxide growth is performed using an AG Associates RTPtool. Recipe is 650° C.; 60 s; Gases: 5 L O₂ and 5 L N₂. Thickness ofthe antifuse is 18±1 Å. Within wafer thickness uniformity should be lessthan 3% (1 sigma).

Maximum queue time between preclean and RTO is four hours. Queue timebetween RTO and Y2 TiN deposition appears not to be critical. AMAT RTOis an alternate tool.

RTO conditions will be adjusted based on diode e-test results(unprogrammed leakage current and time to breakdown).

Step 15: 200 Å TiN Deposition, Second Wiring Layer (Y2):

Tool used is Endura MOCVD or ULVAC PVD can be used. Recipe: IMP TiNwithout bias. The TiN deposition step should not have any pre-sputterclean or bias in order to protect the antifuse oxide. PVD or MOCVD TiNdeposition can be used.

Step 16: 1500 Å W Deposition, Second Wiring Layer (Y2):

The Novellus W tool can be used. The recipe should be the same as X1 Wdeposition in Step 2 but for deposition time. Deposition time adjustedto target 1500 Å. TiN deposited without bias may make the W nucleationprocess sluggish, which is referred to as an incubation time, making theresulting W thickness lower compared to X1 step. W deposition on PVD orMOCVD TiN may behave differently.

Step 17: Y2 Photolithography—Second Wiring Layer Masking:

Photolithography conditions same as X1 photolithography conditions ofStep 3 except dose of 27.5 mJ/cm². CD specification is 0.16±0.02 μm, andoverlay specification is ±60 nm.

Step 18: Y2 Etch—Second Wiring Layer Etch:

1500 Å W and 200 Å TiN must be etched. Etch conditions are the same asX1 etch conditions described in Step 4. CD spec is 0.15±0.02 μm. Gougeinto beer can 1 polysilicon is about 1400 Å.

Step 19: Y2 Fill:

2500 Å HDP oxide fill. Fill conditions are the same as for X1, describedin Step 5.

Step 20: Y2 CMP:

CMP conditions same as for X1, describe in Step 6.

Step 21: Diode 1 (Beer Can 2) TiN Deposition.

The process to deposit 200 Å of TiN is the same as for beer can 1 TiNdeposition, described in Step 7.

Step 22: Diode 1(Upside Down Diode—Beer can 2) Polysilicon Deposition:

To deposit 200 Å N⁺ polysilicon, 2900 Å undoped polysilicon, 700 Å P⁺silicon, and 300 Å undoped silicon, use the ASML SVG tool. Recipe is540° C., 400 mTorr, with remaining conditions detailed in Table 3:

TABLE 3 1.5% 1.5% Step Time Silane Helium BCl₃ PH₃ 200 Å 5e20 N⁺ 19:30500 380 — 40 Si sccm sccm sccm 2900 Å undoped 2:22:40  500 — — — Si sccm700 Å 1e21 P⁺ 15:00 500 700 100 — Si sccm sccm sccm 300 Å undoped 15:45500 — — — Si sccm

Dopant and concentration for in-situ doping, for N⁺ should bephosphorous at 5.0 E20 per cm³. For P⁺, use boron at 1.0 E21 per cm³.Thickness variation is the same as for beer can 1, as described in Step8.

500 Å of the P⁺ thickness and undoped polysilicon is sacrificial for CMPpolishing. About 200 Å of N⁺ and P⁺ polysilicon is required for Ohmiccontact to the underlying TiN/W. The undoped cap eliminates memoryeffect during deposition.

Alternatively, ion implantation can be used instead of in situ dopingfor the N⁺ layer. Such implantation would be done after the beer canCMP.

Step 23: Diode 1 (Beer can 2) Hard Mask Deposition:

To deposit a 400 Å hard mask oxide, the deposition conditions are thesame as for beer can 1 hard mask, described in Step 9. This hard mask isneeded to prevent poor photolithographic profile caused by scannerlimitations from being transferred to the diode at etch. The hard maskalso helps CMP.

Step 24: Diode 1 (Beer can 2) Photolithography:

Beer can 2 photolithography is the same as beer can 1 photolithography,as described in Step 10.

Step 25: Beer Can 2 Etch:

Beer can 2 etch is the same as beer can 1 etch, as described in Step 11.

Step 26: BC2 (Beer can 2) Fill:

Beer can 2 fill is the same as beer can 1 fill, as described in Step 12.

Step 27: Beer Can 2 CMP:

Beer can 2 CMP is the same as beer can 1 CMP, as described in Step 13.

Step 28: Beer Can 2 Antifuse Growth:

To grow 18 Å of antifuse oxide, perform a preclean: 100:1 HF, 45 s. Growthe antifuse using the AG Associates RTP. The recipe is 650° C., 5 l O₂,5 l N₂, 60 s. In beer can 2, antifuse oxide is grown on P⁺ polysiliconas opposed to on N⁺ polysilicon in the case of beer can 1.

RTO conditions will be adjusted based on diode e-test results(unprogrammed leakage current and time to breakdown).

Step 29: X3 TiN 1 Deposition:

To deposit 300 Å of TiN, no preclean is required. The tool and recipefor this TiN deposition are the same as for the Y2 TiN deposition,described in Step 15, except for the deposition time. The depositiontime is compensated for increased thickness

Plasma damage prevention is critical during TiN deposition in order toprotect the antifuse. TiN is needed to protect the antifuse during ziaetch and cleans. 300 Å of TiN is needed to protect the antifuse frombeing exposed during the TiN deposition prior to X3 W deposition.

Step 30: Zia 1 Photolithography:

Use 4620 Å of UV135 resist, and 600 Å of BARC. The scanner is theASML/500 (NA/sigma: 0.48/0.36). Alternatively ASML/700 can be usedinstead. Expose conditions are 31 mJ/cm²/−0.1 μm Focus. CD should be0.21±0.02 μm. Overlay is ±75 nm. 0.21 μm wide zias are targeted. Threedifferent zia lengths exist in the cell. Different lengths can be useddepending on how many memory levels are to be contacted.

Step 31: Zia 1 Etch:

Etch 300 Å TiN and about 14000 Å oxide +25% OE. Etch tool is CenturaMxP-eMax. Etch recipe for BARC/TiN Etch is Ar/CF₄/CHF₃ chemistry. Forthe oxide etch the recipe is Ar/C₄F₆/O₂ chemistry.

The CD specification is 0.21±0.025 μm (this is the top CD.) CD bias<10nm (relative to photolithography for top CD.)

Regarding selectivity, resist loss during TiN etch is 500-600 Å. Oxideto resist selectivity is 6:1. Oxide to W selectivity is 100:1, so thereis no noticeable W loss.

The wall angle is 88±1°. For resist strip, use Gasonics—O₂/N₂ ash; 270°C. Solvent clean is performed using Semitool 10 min EKC Clean.

Note BARC may not be needed on top of TiN. TEL DRM is an alternate toolfor this process.

Zias are rectangular. Zias of three different lengths are present in themask. Selectivity to W during zia etch is very good.

Step 32: X3 TiN 2 Deposition:

Perform the second TiN (200 Å) deposition at X3 using the AMAT Enduratool. The recipe: IMP TiN or, alternatively, MOCVD TiN.

Pre-sputter is equivalent to an oxide loss of 300 Å on a blanket oxidewafer, or a loss of 120 Å of TiN on a blanket TiN wafer.

Pre-sputter step is critical since it serves two competing purposes.That is, W surface at the bottom of the zia should be cleaned of nativeoxide while ensuring that the antifuse oxide is not exposed or damaged.

The total TiN thickness (TiN1+TiN2—pre-sputter) on the wafer is 350-400Å at the end of this step.

Second TiN thickness can be reduced if MOCVD is used.

Step 33: X3 W Deposition:

For 2000 Å W Deposition, use Novellus CVD W tool. No preclean. Recipe isthe same as X1 or Y2 W deposition except for time, which is adjusted forthickness target.

Note that W thickness is 2000 Å. This is required to fill 0.35 μm widezias. If zia size is reduced to below 0.3 μm, W thickness can be reducedto 1500 Å, as in the case of X1 and Y2.

Step 34: X3 Photolithography:

Photolithography conditions and specifications are the same as that ofY2 photolithography steps, described in Step 17. CD specification is0.16±0.02 μm; overlay specification is ±60 nm.

Step 35: X3 Etch: Etch 2000 Å of W and 400 Å of TiN:

Etch and clean conditions and specification are the same as those of X1and Y2 etch steps. Etch times should be adjusted in W and TiN etch stepsto account for increased thickness relative to X1 and Y2. Need to verifyif resist thickness is sufficient to tolerate longer etch relative to X1and Y.

Step 36: X3 Fill: Deposit 3000 Å of HDP Fill Oxide:

Same as X1 and Y2 fill except for thickness. Increased oxide thicknessto account for increased W thickness.

Step 37: RTA: Final Anneal

Use the AG Associates RTA tool. Recipe is 770° C., 60 s; 10 liters Arflow. The purpose is to crystallize silicon and activate dopant.

Step 38: X3 CMP:

Blanket wafer CMP removal target is 1700 Å. Other conditions are thesame as X1 and Y2 CMP, described in Step 6.

Step 39: X3 Cap Oxide Deposition:

Deposit 5000 Å of Silane Oxide using Novellus tool. Recipe is Silaneoxide. This need not be HDP oxide since it is a cap oxide on a CMPedsurface. Can be AMAT oxide or Novellus.

Step 40: Final Zia Photolithography:

The final zia makes contact between top metal and memory layers.

Use ASML /500 (NA/sigma: 0.48/0.36). Photolithography conditions are thesame as Z1 except dose of 30 mJ/cm². CD is 0.21±0.02 μm; overlay is ±75nm.

Step 41: Final Zia Etch:

Etch 600 Å of BARC, 5000 Å of oxide +25% OE. Use Centura MxP eMax tool.Etch chemistry can be the same as Zia 1 etch described in Step 31. TiNetch step should be removed. Oxide etch time should be adjusted totarget 8000 Å of oxide removal. Ash and solvent clean: same as zia 1.described in Step 31. CD Spec is 0.21±0.025 μm. Etch is straightforwardand simple since the stack height is short and W is a good etch stop.Same recipe used for etching zia 1 can be used after removing TiN etchstep and altering time to account for thickness difference.

Step 42: Final Zia TiN Deposition:

Use AMAT Endura tool. Recipe is 200 Å IMP TiN; MOCVD TiN can be used.Recipe conditions can be the same as the TiN deposition condition usedfor second TiN deposition at X3 deposition.

Step 43: Go to Step 44.

Step 44: Final Zia W Deposition:

For 2000 Å W deposition, use the Novellus W tool. The recipe is the sameas for the X3 W deposition described in Step 33. Note that W thicknessis 2000 Å. This is required to fill 0.35 μm zias. If zia size isreduced, W thickness can be reduced accordingly.

Step 45: Final Zia W CMP:

Use IPEC 472. Consumables are Rodel MSW 1500 (KIO₃—alumina) slurry,Politex main polish pad, no buff. Polish rate is about 3000 Å/min.Polish time is 90 seconds. Poor oxide selectivity; oxide loss isapproximately 1000 to 1500 Å. Alternately, any via or contact Wpolishing recipes can be used instead.

Step 46: Top Metal Deposition:

Deposit 150 Å Ti, 4000 Å Al, 300 Å TiN. Use AMAT Endura tool. Recipe:Deposit 150 Å PVD Ti; Presputter is equivalent to 50 Å of oxide. Deposit4000 Å PVD Al at 200° C. Deposit 300 Å PVD TiW. Any top metal stackconditions can be used.

Step 47: Top Metal Photolithography:

Use ASM11. Resist is JSR iX715 DM7 (1.2 μm). BARC: AR2. Photolithographyconditions: 220 mJ/cm²/0.0 μm. CD is 1.0 um±0.1 μm.

Step 48: Top Metal Etch:

Tool: LAM 9600 PTX. Etch recipe is Cl₂/BCl₃/SF₆ BARC and TiW etch.Cl₂/BCl₃ Al etch, OE, and Ti etch.

Use standard plasma strip conditions. Solvent Clean tool is Semitool, 20min EKC-265, 65° C.

Step 49: Alloy:

Use VTR Furnace. Recipe: Alloy at 400° C. and atmospheric pressure for30 minutes in N₂ with about 5% H₂.

Periodic backside removal was found to be necessary to process thewafers through all the photo and etch steps. Stress measurementsindicate linear increase in stress with layer number and stress reliefwith backside film removal. Backside polysilicon removal after everyfourth polysilicon stack deposition would prevent any stress relatedprocessing problems and ensure sufficient process margin. Another optionis to add backside polysilicon removal after every stack depositionstarting with P⁺ polysilicon (as in the case of beer can 1.) This wouldalso alleviate defect concerns.

More backside etches may be necessary to meet particle performance.

Care must be taken in setting up the photolithography job such thatphotolithographic patterning leaves no part of the wafer unexposed (suchas wafer scribe region). W peeling is typically seen in the alignmentmark region and in big pads.

Thick oxide on W and excessive time at high temperature (greater than700° C.) exacerbate W peeling problem.

The foregoing detailed description has described only a few of the manyforms that this invention can take. For this reason, this detaileddescription is intended by way of illustration, and not by way oflimitation. It is only the following claims, including all equivalents,which are intended to define the scope of this invention.

1. A method for forming a monolithic three dimensional memory array, themethod comprising: forming a first plurality of substantially parallel,substantially coplanar conductors above a substrate; forming a firstplurality of semiconductor elements above the first plurality ofsubstantially parallel, substantially coplanar conductors, each of thefirst plurality of semiconductor elements comprising a first heavilydoped layer having a first conductivity type, a second lightly dopedlayer on and in contact with the first heavily doped layer, and a thirdheavily doped layer on and in contact with the second lightly dopedlayer, the third heavily doped layer having a second conductivity typeopposite the first conductivity type; and forming a second plurality ofsubstantially parallel, substantially coplanar conductors above thefirst plurality of semiconductor elements.
 2. The method of claim 1,wherein forming the first plurality of substantially parallel,substantially coplanar conductors comprises: depositing a firstconductive layer; patterning and etching the first conductive layer toform the first plurality of substantially parallel, substantiallycoplanar conductors; depositing a first dielectric material over andbetween the first plurality of substantially parallel, substantiallycoplanar conductors; and planarizing to expose tops of the firstplurality of substantially parallel, substantially coplanar conductorsseparated by the first dielectric material.
 3. The method of claim 2,wherein forming the first plurality of semiconductor elements comprises:after planarizing, depositing a first semiconductor layer stack on thefirst dielectric material and the first plurality of substantiallyparallel, substantially coplanar conductors; patterning and etching thefirst semiconductor layer stack to form the first plurality ofsemiconductor elements; depositing a second dielectric material on andbetween the first plurality of semiconductor elements; and planarizingto expose tops of the first plurality of semiconductor elements.
 4. Themethod of claim 3, wherein depositing the first semiconductor layerstack comprises depositing polycrystalline silicon.
 5. The method ofclaim 1, wherein each of the first plurality of semiconductor elementsis pillar-shaped.
 6. The method of claim 1, wherein the third heavilydoped layer of each of the first plurality of semiconductor elements isdoped by ion implantation.
 7. The method of claim 1, wherein the firstheavily doped layer of each of the first plurality of semiconductorelements is doped by in situ doping.
 8. The method of claim 1, furthercomprising forming a second plurality of semiconductor elements abovethe second plurality of substantially parallel, substantially coplanarconductors.
 9. The method of claim 8, further comprising forming a thirdplurality of substantially parallel, substantially coplanar conductorsabove the second plurality of semiconductor elements.
 10. The method ofclaim 1, further comprising forming a plurality of first antifuse layersdisposed between the first plurality of semiconductor elements and thesecond plurality of substantially parallel, substantially coplanarconductors.
 11. The method of claim 10, wherein forming the firstantifuse layers comprises forming oxide layers.
 12. The method of claim11, wherein forming oxide layers comprises oxidizing a portion of thethird heavily doped layer of each of the first plurality ofsemiconductor elements.
 13. The method of claim 1, wherein the firstconductivity type is N-type and the second conductivity type is P-type.14. The method of claim 1, wherein the first conductivity type is P-typeand the second conductivity type is N-type.